1. Field of the Invention
The invention relates to a calibration device for a programmable tester apparatus that can be inserted into a holding.
2. Description of the Related Art
Electronic circuits, which are used for example for integrated circuits in chips or electronic components, have to be tested before being shipped to the customer. This is done using tester devices which couple in predefined signal sequences to the circuits under test, or the device under test having the electronic circuits, and register and evaluate the corresponding reaction of the devices under test.
In the case of memory testers, which for example test memory chips with regard to their functionality, essentially rising and falling signal edges with a specific temporal succession are passed to a memory chip under test and corresponding signals are coupled out from the memory chip and analysed. A tester arrangement of this type is generally provided with a number of bidirectional tester channels that are led via corresponding adapter sockets to the device under test, here the corresponding memory chip. A tester channel is understood hereinafter to be the means by which test signals are passed to the device and, in the case of bidirectional embodiment, signals also pass from the device to the tester.
In order to be able to test modern, fast memory chips, in particular, synchronization of the many different tester channels by means of which signal edges are coupled into the device under test is very important. In order to test memory accesses, by way of example, rising and falling signal edges have to be applied simultaneously to a specific number of data connections of a memory chip under test. In order that the respective test signal edges arrive simultaneously at the device under test, it is necessary, in the context of test signal or test signal edge generation, to take account of the signal propagation times through cable connections, test sockets, propagation times through to the connecting elements to the connection pins of the device under test in the definition, at the tester end, of the instants at which respective signal edges are generated.
FIG. 4 shows by way of example, an arrangement for testing electronic devices. In this case, a programmable tester device is provided, having a tester mainframe TMF, for generating test signals that are passed via tester channels TKN and holding and contact-making means TK, HFM, DSA, S to a device under test DUT.
In this case, in generally known tester arrangements, the device under test DUT is inserted into a socket S, which is in turn mounted on a device socket adapter DSA. The connection between the actual test head TK, having the driver electronics and comparators for the individual tester channels TKN, and the device socket adapter DSA is effected by a so-called HiFix HFM, which keeps a cabling K ready. In order to take account as far as possible of the entire signal path between the tester mainframe TMF with the test head TK and the device under test DUT in the calibration of the tester channels TKN, various solutions have been proposed in the past.
In a procedure according to the so-called autocalibration AutoCal, a calibration unit (not illustrated here) with drivers and comparators for each tester channel is placed on to the test head TK. It is then possible, through comparison of the arriving signals at a calibration unit of this type, to determine at least the signal propagation time difference between tester channels TKN in the test head TK itself and to compensate for these differences through programming of the tester mainframe. In a procedure according to AutoCal it is not possible, however, to take account of influences through the cabling K in the HiFix HFM, which is required in the actual memory test. A further disadvantage is that docking the calibration unit to the test head TK is time-consuming and thus delays a subsequent tester run. Furthermore, AutoCal affords only low accuracy for the calibration.
In a calibration according to SBCal the device socket adapters DSA have to be replaced by manufactured calibration socket adapters CSA which short-circuit groups of tester channels TKN or cables K of the HiFix with one another. It is thus possible, through suitable programming PRG of the tester mainframe TMF, to detect the signal propagation time by transmitting signal edges into the HiFix HFM and detecting the corresponding signal on the assigned short-circuited tester channel, a propagation time through to the device socket adapter and to compensate for it through suitable programming.
Although SBCal achieves calibration through to the HiFix plane, the calibration outlay as a result of the removal of the device socket adapters and the devices under test is high. Moreover, influences on the signal propagation time within the sockets S and the device socket adapter DSA cannot be taken into account here.
In the case of so-called HiCal, the sockets S are removed from the device socket adapters DSA and the corresponding contacts between device socket adapter DSA and socket S are tapped by means of a robot. This external robot thus measures signals such as would be coupled into the socket S during a test method. By means of the external evaluation in a robot, the tester mainframe TMF can again be manually programmed in such a way that signals coupled into the tester channels TKN arrive simultaneously at least at the device socket adapter DSA. However, the influences of the sockets S on the signal propagation times are left out of consideration in the case of HiCal as well.
The already known possibilities for calibrating the tester channels thus have a series of disadvantages. In comparison with carrying out the test method on the device under test, it is necessary for the signal paths to be altered during the calibration. Additional tester hardware is required for the known calibration methods. Compared with an actual test cycle of the devices, it is necessary to alter the set-up for the calibration, which is time-consuming.